Exemplary embodiments relate generally to pipelined data transfer operations, and particularly to systems and methods for monitoring performance in a shared pipeline.
In computing, a pipeline may be considered as a set of data processing elements connected in series, so that the output of one element is the input of the next one. The elements of a pipeline are often executed in parallel or in time-sliced fashion; in that case, some amount of buffer storage is often inserted between elements.
Further, an instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their instruction throughput (the number of instructions that can be executed in a unit of time). Pipelining involves splitting the processing of a computer instruction into a series of independent steps, with storage at the end of each step. This allows the computer's control circuitry to issue instructions at the processing rate of the slowest step, which is much faster than the time needed to perform all steps at once.
It is frequently the case, for example with early hardware prototypes, that performance characteristics of the system fall short of expectations. Finding out the root cause of performance degradation, e.g., why a pipelined operation is taking longer than expected, is important in improving performance. Often, a processing entity such as a cache controller includes multiple controllers or subcomponents that are responsible for executing different instructions that make up an operation. Caches are typically equipped with a coarse grained counter that measures the time taken between receiving or initiating an operation and operation completion. This counter may be used to indicate that the operation is not making progress and when it is deemed to be truly hung. Tracking down the root of the problem is challenging because often there is not enough information to pinpoint the areas of the controller design that are responsible for the performance degradation.